FRACTIONAL-RATIO FREQUENCY SYNTHESIZER WITH MULTI-PHASE OUTPUT CLOCKS AND METHOD FOR SYNTHESIZING FREQUENCY USING THE SAME

摘要

The present invention relates to a fractional-ratio frequency synthesizer having multi-phase output clocks and a method for synthesizing a frequency using the same. The fractional-ratio frequency synthesizer having the multi-phase output clocks comprises: a forward pass unit to output an output clock having a frequency obtained by multiplying the frequency of the input clock by a natural number or a fraction; a delay control feedback block to generate a control voltage (V_Ctrl) to synchronize the output clock of the forward pass unit with the input clock; and a multiplication control feedback block to generate a control signal (Ctrl[1:0]) for a mode change to be applied to the forward pass unit and the delay control feedback block to multiply the frequency of the input clock of the forward pass unit by a natural number or a fraction. The forward pass unit comprises a voltage control delay line having a plurality of voltage control delay units. Time delays of the voltage control delay units are synchronized with each other to generate multi-phase output clock signals.