INPUT/OUTPUT CIRCUIT

摘要

A circuit includes a first power node configured to carry a voltage K·VDD, a second power node configured to carry a zero reference level, an output node, K P-type transistors serially coupled between the first power node and the output node, and K N-type transistors serially coupled between the second power node and the output node. Gates of the K P-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of source-gate voltages or absolute values of drain-gate voltages are equal to or less than VDD. Gates of the K N-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of gate-source voltages or gate-drain voltages are equal to or less than VDD.

主权项

1. A circuit, comprising:
a first power node configured to carry a first voltage, a voltage level of the first voltage being K·VDD above a zero reference level, VDD being a predetermined, positive value, and K being a positive integer equal to or greater than 3; a second power node configured to carry a second voltage, a voltage level of the second voltage being the zero reference level; an output node; K P-type transistors serially coupled between the first power node and the output node, each of the K P-type transistors being denoted as an i-th transistor of the K P-type transistors, i being an order index ranging from 1 to K, a smaller order index i being used to denote a transistor closer to the first power node, and a gate of the i-th transistor is configured to receive:
a first signal being set at (K−1)·VDD after an input signal is set at the zero reference level and being set at K·VDD after the input signal is set at VDD, when i=1;a second signal being set at (K−1)·VDD, when i=2; anda first set of biasing signals being set at one or more voltage levels in a manner that an absolute value of a source-gate voltage or an absolute value of a drain-gate voltage of the i-th transistor is equal to or less than VDD when i≠1 or 2; and K N-type transistors serially coupled between the second power node and the output node, each of the K N-type transistors being denoted as an j-th transistor of the K N-type transistors, j being an order index ranging from 1 to K, a smaller order index j being used to denote a transistor closer to the second power node, and a gate of the j-th transistor is configured to receive:
a third signal being set at the zero reference level after the input signal is set at the zero reference level and being set at VDD after the input signal is set at VDD, when j=1;a fourth signal being set at VDD when j=2; anda second set of biasing signals being set at one or more voltage levels in a manner that an absolute value of a gate-source voltage or an absolute value of a gate-drain voltage of the j-th transistor is equal to or less than VDD when j≠1 or 2.