EFFICIENT EXTRACTION FOR COLORLESS MULTI PATTERNING

摘要

A method for parasitic capacitance extraction for integrated circuit (IC) designs fabricated involving multiple patterning that includes identifying, at a computing system, metal features in a metal layer of an IC design and generating, at the computing system, a graph based on spacing relationships between the metal features. The method further includes predicting, at the computing system, which metal features are to be formed by the same mask in the multiple patterning lithography process from the graph. The method further can include performing, at the computing system, a parasitic capacitance extraction analysis of the IC design utilizing the prediction of which metal features are to be formed by the same mask, and performing, at the computing system, timing analysis on the IC design utilizing the list of vertices sharing the same designators and the parasitic capacitance extraction calculations.

主权项

1. A computer-implemented method comprising:
identifying, at a computing system, metal features in a metal layer of an integrated circuit design; generating, at the computing system, a graph based on spacing relationships between the metal features; predicting, at the computing system, which metal features are to be formed by a same mask in a multiple patterning lithography process using the graph; and generating, at the computing system, analysis data for the integrated circuit design based on the prediction of which metal features are to be formed by the same mask.