BIAS CIRCUIT FOR A SWITCHED CAPACITOR LEVEL SHIFTER

摘要

A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal.

主权项

1. A noise resistant switched capacitor level shifter, comprising:
a first capacitor; a second capacitor; a first switch coupled to a first terminal of the level shifter and coupled to a first terminal of the first capacitor; a second switch coupled to the first terminal of the first capacitor and coupled to a first terminal of the second capacitor; a third switch coupled to a third terminal of the level shifter and coupled to a second terminal of the first capacitor; a fourth switch coupled to the second terminal of the first capacitor and coupled to a second terminal of the second capacitor; a first AC (alternating current) coupling and DC (direct current) biasing device coupled to a control terminal of the first switch; and a second AC coupling and DC biasing device coupled to a control terminal of the third switch; wherein the first and second devices are configured to DC bias the control terminal of respective first or third switch and to pass an AC coupled, voltage clamped version of a first clock signal to the control terminal of the respective first or third switch, the first and second devices operable to clamp a voltage at the control terminal of respective first or third switch to within a clamping range and wherein the second switch and the fourth switch are configured to couple to a second clock signal.