Low Threshold Voltage and Inversion Oxide Thickness Scaling for a High-K Metal Gate P-Type MOSFET

摘要

A semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.

主权项

1. A semiconductor structure comprising:
a semiconductor substrate comprising a semiconductor material; a p-type field effect transistor (pFET) disposed upon said semiconductor substrate and comprising a semiconductor channel region comprised of SiGe formed upon or within a surface of said semiconductor substrate; a gate dielectric comprising an oxide layer overlying said semiconductor channel region comprised of SiGe and a high dielectric constant (high-k) dielectric layer overlying said oxide layer; a gate electrode overlying said high-k dielectric layer and comprising a lower metal layer abutting said high-k dielectric layer, a scavenging metal layer abutting said lower metal layer, and an upper metal layer abutting said scavenging metal layer, wherein said scavenging metal layer includes a metal (M) for which the Gibbs free energy change of the chemical reaction, in which a silicon atom combines with a metal oxide material including said scavenging metal and oxygen to form said scavenging metal in elemental form and silicon dioxide, is positive; and an n-type field effect transistor (nFET) disposed upon said semiconductor substrate and comprising a semiconductor channel region comprised of Si, where a gate electrode of said nFET also comprises said scavenging metal layer, and wherein a high temperature anneal is performed of the semiconductor structure in an oxygen ambient forming a metal oxide of the scavenging metal layer, wherein the scavenging metal layer is more prone to forming a metal oxide than the upper metal layer and the lower metal layer and forms the metal oxide within the scavenging layer by scavenging impurity oxygen atoms that diffuse through the upper metal layer toward the high-k dielectric layer and scavenges oxygen from the oxide layer as oxygen atoms migrate towards the oxide layer from below or from the side of the oxide layer to limit growth of the oxide layer during the high temperature anneal in oxygen ambient.