发明名称 |
VOLTAGE CONVERSION CIRCUIT AND ELECTRONIC CIRCUIT |
摘要 |
A voltage conversion circuit includes: a first voltage conversion unit configured to perform voltage conversion on an input signal, the voltage conversion causing a predetermined delay time, and supply a resultant signal as a first converted signal; a second voltage conversion unit configured to perform voltage conversion on the input signal, the voltage conversion causing a delay time that is different from the predetermined delay time, and supply a resultant signal as a second converted signal; and an output unit configured to generate and output an output signal corresponding to the first and second converted signals in a matching period of time in which voltages of the first converted signal and the second converted signal are matched with each other, and continuously output the output signal in a period of time excluding the matching period of time, the output signal being output in the matching period of time. |
申请公布号 |
US2015244266(A1) |
申请公布日期 |
2015.08.27 |
申请号 |
US201514608293 |
申请日期 |
2015.01.29 |
申请人 |
Sony Corporation |
发明人 |
Tsukuda Yasunori;Yagishita Yuki |
分类号 |
H02M3/158 |
主分类号 |
H02M3/158 |
代理机构 |
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代理人 |
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主权项 |
1. A voltage conversion circuit, comprising:
a first voltage conversion unit configured to perform voltage conversion on an input signal, the voltage conversion causing a predetermined delay time, and supply a resultant signal as a first converted signal; a second voltage conversion unit configured to perform voltage conversion on the input signal, the voltage conversion causing a delay time that is different from the predetermined delay time, and supply a resultant signal as a second converted signal; and an output unit configured to generate and output an output signal corresponding to the first converted signal and the second converted signal in a matching period of time in which a voltage of the first converted signal and a voltage of the second converted signal are matched with each other, and continuously output the output signal in a period of time excluding the matching period of time, the output signal being output in the matching period of time. |
地址 |
Tokyo JP |