发明名称 SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME
摘要 A semiconductor memory device comprises a memory cell array. The memory cell array comprises a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines. The memory cells are stacked in a direction perpendicular to a substrate, and each memory cell comprises a variable resistance element. The semiconductor memory device also includes a select transistor layer comprising a plurality of select transistors, each select transistor being operative to select any one of the first wiring lines or one of the second wiring lines. Two select transistors are connected to two different respective first wiring lines, stacked in a direction perpendicular to the substrate, and configured to share one gate electrode.
申请公布号 US2015243887(A1) 申请公布日期 2015.08.27
申请号 US201414578714 申请日期 2014.12.22
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SAITOH Masumi;TANAKA Chika;SUGIMAE Kikuko;KONNO Takuya
分类号 H01L45/00;H01L27/24 主分类号 H01L45/00
代理机构 代理人
主权项 1. A semiconductor memory device comprising: a memory cell array, the memory cell array comprising a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines, the memory cells being stacked in a direction perpendicular to a substrate, each memory cell comprising a variable resistance element; and a select transistor layer comprising a plurality of select transistors, each select transistor being operative to select any one of the first wiring lines or one of the second wiring lines, two select transistors being connected to two different respective first wiring lines, and being stacked in a direction perpendicular to the substrate, and the two select transistors being configured to share one gate electrode.
地址 Minato-ku JP