发明名称 |
MODELESS INSTRUCTION EXECUTION WITH 64/32-BIT ADDRESSING |
摘要 |
In an aspect, a processor supports modeless execution of 64 bit and 32 bit instructions. A Load/Store Unit (LSU) decodes an instruction that without explicit opcode data indicating whether the instruction is to operate in a 32 or 64 bit memory address space. LSU treats the instruction either as a 32 or 64 bit instruction in dependence on values in an upper 32 bits of one or more 64 bit operands supplied to create an effective address in memory. In an example, a 4 GB space addressed by 32-bit memory space is divided between upper and lower portions of a 64-bit address space, such that a 32-bit instruction is differentiated from a 64-bit instruction in dependence on whether an upper 32 bits of one or more operands is either all binary 1 or all binary 0. Such a processor may support decoding of different arithmetic instructions for 32-bit and 64-bit operations. |
申请公布号 |
US2015242212(A1) |
申请公布日期 |
2015.08.27 |
申请号 |
US201514612090 |
申请日期 |
2015.02.02 |
申请人 |
Imagination Technologies Limited |
发明人 |
Sudhakar Ranganathan;Rozario Ranjit J |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
1. A method implemented in a processor, comprising:
receiving, in an address calculation unit, a value expressed by a number of bits equal to a width of general-purpose registers in the processor; determining whether the value is within any of a set of pre-determined numerical ranges, and responsively performing an arithmetic operation using only a least significant portion of the value, the least significant portion having a pre-determined number of bits, and sign-extending a result of the arithmetic operation to the width of the general-purpose registers; and using the sign-extended result as an effective address for executing the instruction. |
地址 |
Kings Langley GB |