High-Speed Address Fault Detection Using Split Address ROM

摘要

High-speed address fault detection is described that uses a split address ROM (read only memory) for address fault detection in split array memory systems. In one aspect, a disclosed embodiment includes separate arrays of memory cells having a plurality of wordlines and being configured to be accessed based upon a wordline address. Two or more separate address ROMs are also provided with each address ROM being associated with a different one of the separate arrays and being configured to provide outputs based upon only a portion of the wordline address. Detection logic is coupled to the outputs from the address ROMs and is configured to provide one or more fault indicator outputs to indicate whether an address fault associated with the wordline address has occurred. The outputs form the address ROMs can also be used for wordline continuity fault detection. Other embodiments are also described.

主权项

1. A memory system having address fault detection, comprising:
at least two separate arrays of memory cells having a plurality of wordlines; at least two separate address ROMs (read only memories), each address ROM being associated with a different one of the at least two separate arrays of memory cells and being configured to provide outputs based upon only a portion of a wordline address used to select one of the wordlines; and detection logic coupled to the outputs of the address ROMs and configured to provide at least one fault indicator output to indicate when at least one address fault associated with the wordline address has occurred.