CDR VOTER WITH IMPROVED FREQUENCY OFFSET TOLERANCE

摘要

An improved clock data recovery circuit is provided which provides lower bit error rates and faster locking times. In an embodiment, the circuit includes a voter having one or more voter inputs. The voter may generate up votes indicative of a recovered clock having a negative phase offset relative to a given voter input, or down votes indicative of the recovered clock having a positive phase offset. The circuit may include a comparator configured to output a phase adjustment signal and a tie signal. The circuit may further include an M-depth shift register and a multiplexer configured to select either the phase adjustment signal or an output from the shift register as a multiplexer output. The circuit may further include a flip-flop that generates a phase adjustment output signal. The shift register may receive the phase adjustment output signal at a data input of the shift register.

主权项

1. A circuit comprising:
a voter having one or more voter inputs, the voter generating, for each given voter input, an up vote indicative of a recovered clock having a negative phase offset relative to the given voter input, or a down vote indicative of the recovered clock having a positive phase offset relative to the given voter input; a comparator coupled to the voter configured to output a phase adjustment signal and a tie signal based upon the up and down votes generated; a shift register including one or more flip-flops; a multiplexer coupled to the comparator and the shift register, the multiplexer configured to select either the phase adjustment signal or an output from the shift register as a multiplexer output, based on the tie signal; and a flip-flop receiving the multiplexer output at a data input of the flip-flop, the flip-flop generating a phase adjustment output signal, the shift register receiving the phase adjustment output signal at a data input of the shift register.