| 发明名称 |
CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD |
| 摘要 |
A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide. |
| 申请公布号 |
US2015243660(A1) |
申请公布日期 |
2015.08.27 |
| 申请号 |
US201414189509 |
申请日期 |
2014.02.25 |
| 申请人 |
STMICROELECTRONICS, INC. ;INTERNATIONAL BUSINESS MACHINES CORPORATION ;GLOBALFOUNDRIES INC. |
发明人 |
LIU Qing;CAI Xiuyu;YEH Chun-chen;XIE Ruilong |
| 分类号 |
H01L27/092;H01L21/285;H01L21/02;H01L29/45;H01L21/8238 |
主分类号 |
H01L27/092 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for fabricating a CMOS integrated circuit structure, comprising:
creating one or more n-type wells; creating one or more p-type wells; creating one or more pFET source-drains embedded in and overlaying each of the one or more n-type wells,
wherein a material of each of the one or more pFET source-drains comprises silicon doped with a p-type material; creating one or more nFET source-drains embedded in and overlaying each of the one or more p-type wells,
wherein a material of each of the one or more nFET source-drains comprises silicon doped with an n-type material; creating a pFET contact overlaying each of the one or more pFET source-drains,
wherein a material of each pFET contact comprises nickel silicide; and creating an nFET contact overlaying each of the one or more nFET source-drains,
wherein a material of each nFET contact comprises titanium silicide. |
| 地址 |
Coppell TX US |
