发明名称 INRUSH CURRENT SUPPRESSION CIRCUIT
摘要 This inrush current suppression circuit suppresses an inrush current flowing to a load, and the load is provided with an input capacitor (10) connected to a power supply (1), and a pair of output terminals (3, 4), which are connected in parallel to the input capacitor (10), and which output a current inputted from the power supply (1). The inrush current suppression circuit is configured from: a FET (5) that is on/off controlled by being connected to the direct current power supply (1); a first inductor (8) connected between a connection point and the FET (5); a reflux diode (9) that connects the cathode to a connection point between the FET (5) and the first inductor (8); and a second inductor connected between the connection point and the anode of the diode. The first and second inductors (8) are configured from a magnetic body covering around an electric wire (L), i.e., a current path.
申请公布号 WO2015125793(A1) 申请公布日期 2015.08.27
申请号 WO2015JP54346 申请日期 2015.02.17
申请人 YAZAKI CORPORATION 发明人 MATSUSHITA YOSHINORI;KIMURA OSAMU
分类号 H02H9/02;H02J1/00 主分类号 H02H9/02
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