发明名称 DUTY CYCLE CONTROLLER
摘要 In one aspect, a duty cycle controller includes a first port configured to receive a voltage bias signal, a second port configured to receive an input voltage signal, a third port configured to provide an output signal of the duty cycle controller having a duty cycle and a n-bit digital-to-analog converter (DAC) configured to receive the voltage bias signal and to provide a DAC output signal to a comparator. The DAC output signal has a peak value. The duty cycle controller also includes the comparator configured to compare the DAC output signal from the n-bit DAC with the input voltage signal to provide a comparator output signal. The comparator output signal is used to provide the output signal of the duty cycle controller and the duty cycle changes with changes to the input voltage signal.
申请公布号 US2015244353(A1) 申请公布日期 2015.08.27
申请号 US201414187545 申请日期 2014.02.24
申请人 Allegro Microsystems, LLC 发明人 Humphrey George P.;Martin William E.
分类号 H03K3/017;H03M1/78 主分类号 H03K3/017
代理机构 代理人
主权项 1. A duty cycle controller comprising: a first port configured to receive a voltage bias signal; a second port configured to receive an input voltage signal; a third port configured to provide an output signal of the duty cycle controller having a duty cycle; a n-bit digital-to-analog converter (DAC) configured to receive the voltage bias signal and to provide a DAC output signal to a comparator, the DAC output signal having a peak value; and the comparator configured to compare the DAC output signal from the n-bit DAC with the input voltage signal to provide a comparator output signal, wherein the comparator output signal is used to provide the output signal of the duty cycle controller, and wherein the duty cycle changes with changes to the input voltage signal.
地址 Worcester MA US