发明名称 VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION
摘要 Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.
申请公布号 KR20150097500(A) 申请公布日期 2015.08.26
申请号 KR20157015582 申请日期 2013.06.24
申请人 INTEL CORP. 发明人 DOYLE BRIAN S.;KOTLYAR ROZA;SHAH UDAY;KUO CHARLES C.
分类号 H01L29/66;H01L21/02;H01L29/06;H01L29/16;H01L29/775 主分类号 H01L29/66
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