| 摘要 |
An adaptive clock generation circuit for synthesizing Time-Average-Frequency in dynamic fashion includes (a) a timing circuit for generating a base unit of fixed time span, (b) a control circuit that takes inputs from a microelectronic system wherein the control circuit and the clock generation circuit reside, for generating a update signal and a frequency control word, (c) a direct period synthesizer for generating a plurality of types of pulses by utilizing said base unit and the frequency control word, for creating a segment of a clock pulse train by connecting electrical pulses in series that are selected from said plurality of types according to the update signal, for creating the entire clock pulse train by connecting said segment in series. The resulting Time-Average-Frequency of the clock pulse train matches a selected frequency that is required by the operation of the microelectronic system wherein the clock generation circuit resides. A method of creating such adaptive clock generation circuit is also presented. |
| 主权项 |
1. A clock generation device, comprising:
an input for receiving a signal responsive to environmental change; an output for delivering a clock signal; a signal processing circuit for generating a signal of system status change, having an output for delivering said signal of system status change, said signal processing circuit generates said signal of system status change based on status change of a microelectronic system driven by said clock generation device; a control circuit for generating a signal of update (F), having an output for delivering said signal of update (F), having a first input for receiving said signal of system status change, having a second input for receiving said signal responsive to environmental change, said control circuit generates said signal of update (F) based on said signal of system status change and said signal responsive to environmental change; a base time unit generation circuit for generating a base time unit Δ, having an output for delivering said base time unit Δ; a dynamic direct period synthesis circuit for generating a Dynamic-Time-Average-Frequency (DTAF) clock signal, having a first input for receiving said base time unit Δ from said base time unit generation circuit, having a second input for receiving said signal of update (F) from said control circuit, having an output for delivering said DTAF clock signal, said DTAF clock signal is a clock pulse train consisting of a plurality of segments, each said segment consists of δ clock cycles where δ is an integer of greater than zero, each said segment of said DTAF clock signal comprises δ electrical pulses, said electrical pulses in each said segment can have different length-in-times, length-in-time of each said electrical pulse is equal to an integer multiple of said base time unit A, said integer has a value of greater than one and is determined by said signal of update (F); wherein said output is connected to the output of said dynamic direct period synthesis circuit. |
