发明名称 Fault tolerant apparatus and method for elliptic curve cryptography
摘要 A fault tolerant apparatus and method for elliptic curve cryptography. For example, one embodiment of a processor includes one or more cores to execute instructions and process data; and fault attack logic to ensure that the execution of the instructions and processing of the data is not vulnerable to memory safe-error attacks after a fault is injected by hiding any correlation between processor behavior and secret bits in a secret key.
申请公布号 US9118482(B2) 申请公布日期 2015.08.25
申请号 US201314039997 申请日期 2013.09.27
申请人 INTEL CORPORATION 发明人 Ghosh Santosh
分类号 H04L9/30;G06F12/14 主分类号 H04L9/30
代理机构 Nicholson De Vos Webster & Elliott LLP 代理人 Nicholson De Vos Webster & Elliott LLP
主权项 1. A processor comprising: one or more cores to execute instructions and process data; and fault attack logic to ensure that the execution of the instructions and processing of the data is not vulnerable to memory safe-error attacks by hiding any correlation between processor behavior and secret bits in a secret key, wherein the secret key comprises a secret key [d] based on an elliptic curve defined by Q=[d]P where Q and P are two points on the elliptic curve and [d] is an integer; wherein the fault attack logic is to hide any correlation between processor behavior and secret bits in the secret key by performing register write operations for updating registers for Q0 and Q1 concurrently, on a common clock edge to restore both PA and PD results.
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