| 主权项 |
1. A method of hardware description language simulation for a circuit design, the method comprising:
generating, from the circuit design and using a processor, a simulation executable, wherein generating the simulation executable comprises:
translating, using the processor, hardware description language code comprising a first net sensitivity range of a net that partially overlaps a second net sensitivity range of the net into hardware description language code where the first net sensitivity range is split into at least two net sensitivity ranges at a location determined from a starting index of the second net sensitivity range and where the net sensitivity ranges resulting from the split do not partially overlap the second net sensitivity range;wherein each net sensitivity range defines a subset of signals of the net that a process of the circuit design depends upon;constructing, using the processor, a net sensitivity tree comprising hierarchically ordered nodes;wherein each node specifies a net sensitivity range of the net subsequent to the translation;generating, using the processor, a transaction function for the net of the circuit design as part of the simulation executable, wherein the transaction function is configured to implement a search process defined by the net sensitivity tree; and during execution of the simulation executable, scheduling execute functions of the simulation executable by determining whether to resume execute functions comprising procedural logic of the circuit design that are dependent upon a changed value of at least one signal of the net according to the search process by execution of the transaction function using the processor. |
