Method and system for a gallium nitride vertical JFET with self-aligned source and gate

摘要

A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.

主权项

1. A method for fabricating a vertical JFET, the method comprising:
providing a III-nitride substrate of a first conductivity type; forming a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate; forming a second III-nitride epitaxial layer of the first conductivity type coupled to the first III-nitride epitaxial layer; forming a first masking layer coupled to the second III-nitride epitaxial layer; removing at least a portion of the first masking layer and the second III-nitride epitaxial layer to expose a vertical sidewall of the second III-nitride epitaxial layer and a horizontal surface of the first III-nitride epitaxial layer; forming a spacer coupled to the vertical sidewall of the second III-nitride epitaxial layer and the horizontal surface of the first III-nitride epitaxial layer; and removing at least a portion of the first III-nitride epitaxial layer to form a channel region of the vertical JFET, wherein the spacer is used as a mask to prevent removal of at least a portion of the horizontal surface of the first III-nitride epitaxial layer.