发明名称 |
Memory cell with volatile and non-volatile storage |
摘要 |
The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND, VDD) and comprising a control terminal coupled to said output; a first resistance switching element (102) coupled in series with said third transistor and programmed to have one of first and second resistances (Rmin, Rmax) representing a non-volatile data bit; a fourth transistor (118) coupled between said storage node (112) a second supply voltage (VDD, GND); and control circuitry (130) adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said storage node, and to control said fourth transistor to couple said storage node to said second supply voltage during said transfer phase. |
申请公布号 |
US9117521(B2) |
申请公布日期 |
2015.08.25 |
申请号 |
US201214126067 |
申请日期 |
2012.06.14 |
申请人 |
Centre National de la Recherche Scientifique;Université Montpellier 2 |
发明人 |
Guillemenet Yoann;Torres Lionel |
分类号 |
G11C11/00;G11C13/00;G11C11/16;G11C14/00 |
主分类号 |
G11C11/00 |
代理机构 |
Kaplan Breyer Schwarz & Ottesen, LLP |
代理人 |
Kaplan Breyer Schwarz & Ottesen, LLP |
主权项 |
1. A non-volatile memory element comprising:
first and second transistors forming an inverter coupled between a first storage node and an output of the memory element; a third transistor coupled between the first storage node and a first supply voltage and comprising a control terminal coupled to said output; a first resistance switching element coupled in series with said third transistor and programmed to have one of first and second resistances representing a non-volatile data bit; a fourth transistor coupled between said first storage node and a second supply voltage; and control circuitry adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said first storage node, and to control said fourth transistor to couple said first storage node to said second supply voltage during said transfer phase. |
地址 |
FR |