发明名称 Bus connection circuit, semiconductor device and operation method of bus connection circuit for making procedure for switching between a 1-cycle transfer and a 2-cycle transfer unnecessary
摘要 A bus connection circuit connects a bus master and a plurality of bus slaves. The bus connection circuit includes a mirror area access detecting circuit and a processing circuit. The mirror area access detecting circuit detects that the bus master accesses a mirror area of a first bus slave of the plurality of bus slaves, and output a detection signal based on a detection result. The processing circuit executes processing preset in correspondence to the detection result, to an area or data as an access object, based on the detection result.
申请公布号 US9116783(B2) 申请公布日期 2015.08.25
申请号 US201213659183 申请日期 2012.10.24
申请人 Renesas Electronics Corporation 发明人 Koido Yasuhiro
分类号 G06F13/00 主分类号 G06F13/00
代理机构 Sughrue Mion, PLLC 代理人 Sughrue Mion, PLLC
主权项 1. A bus connection circuit which connects a bus master and a plurality of bus slaves, comprising: a mirror area access detecting circuit configured to detect that said bus master accesses a mirror area of a first bus slave of said plurality of bus slaves, and output a detection signal based on a detection result; and a processing circuit configured to execute preset processing to an area or data as an access object, the preset processing corresponding to the detection result.
地址 Kanagawa JP