| 发明名称 |
Single sided bit line restore for power reduction |
| 摘要 |
A memory circuit to reduce active power is disclosed (FIG. 7). The circuit includes a sense amplifier (600). A first bit line (BL) is coupled to a memory array. A second bit line (BLB) that is a complementary bit line to the first bit line is also coupled to the memory array. A first transistor (TG) is coupled between the first bit line (BL) and the sense amplifier. A second transistor (TG) is coupled between the second bit line (BLB) and the sense amplifier. A first drive circuit (700) is coupled between the sense amplifier and the first bit line and is operable to drive a first data signal from the sense amplifier onto the first bit line when the second transistor is off. |
| 申请公布号 |
US9117535(B2) |
申请公布日期 |
2015.08.25 |
| 申请号 |
US201314063628 |
申请日期 |
2013.10.25 |
| 申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Madan Sudhir K.;McAdams Hugh P. |
| 分类号 |
G11C8/08;G11C11/22;G11C17/12 |
主分类号 |
G11C8/08 |
| 代理机构 |
|
代理人 |
Keagy Rose Alyssa;Cimino Frank D. |
| 主权项 |
1. A memory circuit, comprising:
a sense amplifier; a first bit line coupled to a memory array; a second bit line coupled to the memory array, wherein the second bit line is arranged as a complementary bit line to the first bit line; a second transistor having a current path between the sense amplifier and the second bit line; and a first drive circuit coupled between the sense amplifier and the first bit line and operable to drive a first data signal from the sense amplifier onto the first bit line when the second transistor is off. |
| 地址 |
Dallas TX US |
