Systems and methods for reducing interrupt latency

摘要

Systems, methods, and other embodiments associated with reducing interrupt latency are described. According to one embodiment, an apparatus includes a buffer storing instructions awaiting execution by an execution device. The apparatus also includes an interrupt logic that, in response to receiving an interrupt, classifies instructions as either safe or unsafe. An unsafe instruction will cause the instructions to execute in a manner inconsistent with an instruction set architecture. The interrupt logic also establishes an interrupt boundary between safe and unsafe instructions, and causes the interrupt to be processed at the interrupt boundary such that the interrupt is processed before processing of the unsafe instructions.

主权项

1. An apparatus, comprising:
an interrupt logic configured, in response to receiving an interrupt, to:
i) classify instructions in a buffer awaiting execution by an execution device as either safe or unsafe, wherein an instruction is classified as unsafe when processing the interrupt prior to executing the instruction will cause the instruction to execute in a manner inconsistent with an instruction set architecture;ii) establish an interrupt boundary between safe and unsafe instructions; andiii) cause the interrupt to be processed at the interrupt boundary such that the interrupt is processed before processing of the unsafe instructions.