Multistage voltage regulator circuit

摘要

Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.

主权项

1. A multistage voltage regulator circuit comprising:
a first stage, the first stage comprising:
a first circuit module including a first plurality of memory cells of a first memory array, the first circuit module including a first voltage supply terminal;a first regulated node, the first regulated node is connected to the first voltage supply terminal of the first circuit module to supply a first supply voltage to the first voltage supply terminal, wherein current flowing through the first voltage supply terminal supplies power to the first plurality of memory cells; anda first bias transistor including a first current terminal coupled to a first power supply terminal and a second current terminal coupled to the first regulated node; a second stage, the second stage comprising:
a second circuit module including a second plurality of memory cells of a second memory array, the second circuit module including a second voltage supply terminal;a second regulated node, the second regulated node is connected to the second voltage supply terminal of the second circuit module to supply a second supply voltage to the second voltage supply terminal, wherein current flowing through the second voltage supply terminal of the second circuit module supplies power to the second plurality of memory cells; anda second bias transistor including a first current terminal coupled to the first power supply terminal and a second current terminal coupled to the second regulated node; a bias stage, the bias stage comprising:
a third node, anda third bias transistor including a first current terminal coupled to the first power supply terminal and a second current terminal coupled to the third node; and a control loop for regulating the first supply voltage of the first regulated node and the second supply voltage of the second regulated node, wherein the control loop includes the first bias transistor, the second bias transistor, the third bias transistor, the first regulated node, the second regulated node, and the third node, wherein the control loop includes a coupling of a control terminal of the first bias transistor to the second regulated node, and wherein the control loop further includes a coupling of the first regulated node to a control terminal of the third bias transistor.