Maintaining synchronization during vertical blanking

摘要

Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.

主权项

1. An apparatus, comprising:
a source processor; and a sink processor coupled to the source processor through a primary link and an auxiliary link; wherein the source processor is configured to:
send a wake-up command to the sink processor via the auxiliary link;negotiate one or more component capabilities of the sink processor via an interface that includes the primary link and the secondary link;exchange one or more parameters with the sink processor dependent upon the one or more component capabilities;send a plurality of initialization parameters to the sink processor via the primary link; andsend a synchronization signal to the sink processor via the primary link;send a sleep command to the sink processor via the primary link responsive to the sending of the synchronization signal; wherein the plurality of initialization parameters include a clock data recovery lock parameter, and an idle parameter.