Hierarchical arbitration

摘要

Systems and methods for increasing speed and reducing area for arbitration logic in an integrated circuit (IC) are provided. For example, in one embodiment, a method includes arbitrating at least one master request in a first level of arbitration blocks. A second level of arbitration blocks arbitrates at least two arbitration blocks from the first level. A first level of multiplexers multiplex at least one master payload based at least in part upon the arbitration of the first level of arbitration blocks. A second level of multiplexers multiplex at least two signals propagated from the first level of multiplexers.

主权项

1. A method of arbitrating a plurality of masters in an integrated circuit (IC), the method comprising:
arbitrating, via at least two arbitration blocks in a first level of arbitration blocks, at least two master requests in the IC; arbitrating, via at least one arbitration block in a second level of arbitration blocks, at least two output signals of the first level arbitration blocks; multiplexing, via at least two multiplexers in a first level of multiplexers, at least two master payloads in the IC based at least in part upon the arbitration of the first level of arbitration blocks; and multiplexing, via at least one multiplexer in a second level of multiplexers, at least two signal payloads propagated from the first level of multiplexers.