System and method to predict chip IDDQ and control leakage components

摘要

A method for predicting and controlling leakage wherein an IDDQ prediction macro is placed in a plurality of design topographies and data is collected using the IDDQ prediction macro. The IDDQ prediction macro is configured to measure subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines using the IDDQ prediction macro and establish a leakage model. The method correlates the semiconductor test site measurements and the scribe line measurements to establish scribe line control limits, predicts product leakage; and sets subthreshold leakage limits and gate leakage limits for each product using the leakage model.

主权项

1. A method for creating a leakage model, comprising:
placing an integrated circuit quiescent current (IDDQ) prediction macro in a plurality of design topographies, the IDDQ prediction macro being a design topography comprising same device types as the plurality of design topographies and in a same relative percentage as the plurality of design topographies; collecting data using the IDDQ prediction macro; measuring subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines of the IDDQ prediction macro; establishing the leakage model; correlating the semiconductor test site measurements to the scribe line measurements to establish scribe line control limits; predicting product leakage; and setting subthreshold leakage limits and gate leakage limits for each product using the leakage model.