Resistance change memory

摘要

According to one embodiment, a memory includes memory cells between first conductive lines and second conductive lines. A control circuit is configured to apply a first potential to a first end of a selected first conductive line connected to the selected memory cell among the first conductive lines and first ends of unselected second conductive lines not connected to the selected memory cell among the second conductive lines, apply a second potential larger than the first potential to a first end of a selected second conductive line connected to the selected memory cell among the second conductive lines, apply third potentials smaller than the second potential to first ends of unselected first conductive lines not connected to the selected memory cell among the first conductive lines respectively, and change values of the third potentials based on an address of the selected first conductive line.

主权项

1. A resistance change memory comprising:
a plurality of first conductive lines extending in a first direction, and arranged side by side in a second direction which intersects the first direction; a plurality of second conductive lines extending in the second direction, and arranged side by side in the first direction; memory cells connected between the first conductive lines and the second conductive lines, at respective intersections of the first conductive lines and the second conductive lines; a first driver/decoder connected to first ends of the first conductive lines; a second driver/decoder connected to first ends of the second conductive lines; a potential generating circuit generating a potential which is applied to the first ends of the first conductive lines and the first ends of the second conductive lines; and a control circuit controlling an operation mode which applies a voltage or a current to a selected memory cell among the memory cells, wherein each of the memory cells comprises a rectifying element and a resistance change element connected in series, and the control circuit is configured, in the operation mode, to: apply a first potential to a first end of a selected first conductive line connected to the selected memory cell among the first conductive lines and first ends of unselected second conductive lines not connected to the selected memory cell among the second conductive lines, apply a second potential larger than the first potential to a first end of a selected second conductive line connected to the selected memory cell among the second conductive lines, apply third potentials smaller than the second potential to first ends of unselected first conductive lines not connected to the selected memory cell among the first conductive lines respectively, and change the third potentials to a plurality of values based on an address of the selected first conductive line.