发明名称 |
Memory write assist |
摘要 |
A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell. |
申请公布号 |
US9117500(B2) |
申请公布日期 |
2015.08.25 |
申请号 |
US201414168331 |
申请日期 |
2014.01.30 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
Wu Jui-Jen;Lu Shau-Wei;Lo Robert;Li Kun-Hsi |
分类号 |
G11C7/10;G11C11/412;G11C11/413 |
主分类号 |
G11C7/10 |
代理机构 |
Lowe Hauptman & Ham, LLP |
代理人 |
Lowe Hauptman & Ham, LLP |
主权项 |
1. A write assist cell comprising:
a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation; and a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. |
地址 |
TW |