发明名称 Memory device comprising programmable command-and-address and/or data interfaces
摘要 A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
申请公布号 US9117496(B2) 申请公布日期 2015.08.25
申请号 US201313753360 申请日期 2013.01.29
申请人 RAMBUS INC. 发明人 Shaeffer Ian;Lai Lawrence;Ho Fan;Secker David A.;Richardson Wayne S.;Bansal Akash;Leibowitz Brian S.;Oh Kyung Suk
分类号 G11C5/06;G11C5/04;G11C7/10;H01L23/00;H01L25/065 主分类号 G11C5/06
代理机构 Park, Vaughan, Fleming & Dowler LLP 代理人 Park, Vaughan, Fleming & Dowler LLP ;Sahasabuddhe Laxman
主权项 1. A memory device, comprising: a first and second command-and-address (CA) interface; and circuitry to: select an operational mode, wherein both the first and second CA interfaces are active in a first operational mode, and wherein only one of the first or second CA interface is active in a second operational mode, andselect the first or second CA interface as the active CA interface in the second operational mode; wherein the memory device is capable of supporting multiple microthreads in the first operational mode, and wherein the memory device is capable of supporting only a single microthread in the second operational mode.
地址 Sunnyvale CA US