发明名称 Semiconductor device and fabricating method thereof
摘要 A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.
申请公布号 US9117910(B2) 申请公布日期 2015.08.25
申请号 US201414313435 申请日期 2014.06.24
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Jeong Heedon;Chung Jae Yup;Kang Heesoo;Kim Donghyun;Hong Sanghyuk;Hong Soohun
分类号 H01L29/66;H01L29/78 主分类号 H01L29/66
代理机构 Lee & Morse, P.C. 代理人 Lee & Morse, P.C.
主权项 1. A semiconductor device, comprising: a fin region with a long side and a short side; a first field insulating layer including a top surface lower than a top surface of the fin region, the first field insulating layer being adjacent to a side surface of the short side of the fin region; a second field insulating layer including a top surface lower than the top surface of the fin region, the second field insulating layer being adjacent to a side surface of the long side of the fin region; an etch barrier pattern on the first field insulating layer; a first gate on the fin region and the second field insulating layer, the first gate facing the top surface of the fin region and a side surface of the long side of the fin region; a second gate on the etch barrier pattern, the second gate being in an overlapping relationship with the first field insulating layer; and a source/drain region between the first gate and the second gate, the source/drain region being in contact with the etch barrier pattern.
地址 Suwon-si, Gyeonggi-do KR