DATA CACHE PREFETCH CONTROLLER

摘要

A processor includes a processing unit, a memory, a data cache, an One Block Look-ahead (OBL) prefetch engine, a Stride-Allocate on Miss (AoM) prefetch engine and a prefetch back-off module. The prefetch back-off module assigns and sets a status bits to a prefetched cache line and resets the status bit when the cache line is used by the processing unit. The back-off module also decrements a count value when at least two cache lines are used consecutively by the processing unit, increments the count value when at least two unused cache lines are evicted consecutively from the data cache, and disables cache line prefetching when the count value is greater than zero. The stride-AoM prefetch engine includes a reference pattern table (RPT) that stores details of only those instructions that have undergone a cache miss.

主权项

1. A processor, comprising:
a processing unit that executes instructions; a memory, coupled to the processing unit, that stores data required for executing the instructions; a data cache, coupled to the processing unit and the memory, that temporarily stores the instruction data in the form of a plurality of cache lines, wherein each cache line includes a memory address and corresponding data prefetched from the memory; a prefetch engine module, coupled to the processing unit and the data cache, that prefetches the memory address and corresponding data for each cache line from the memory to the data cache; and a prefetch back-off module, coupled to the data cache and the prefetch engine module, that includes:
a control unit that (i) assigns a status bit to a cache line having data newly prefetched into the data cache by the prefetch engine module, (ii) sets the status bit, (iii) resets the status bit when the cache line is used by the processing unit, (iv) identifies cache lines that are used by the processing unit for executing the instructions, (v) and identifies unused cache lines that are evicted from the data cache;a counter that (i) decrements a count value when the control unit identifies at least two prefetched cache lines that are used consecutively by the processing unit, and (ii) increments the count value when the control unit identifies at least two unused prefetched cache lines that are evicted consecutively from the data cache; anda prefetch disabling module, connected to the counter, that disables prefetching of at least one cache line into the data cache when the count value is greater than zero.