| 摘要 |
A constrained turbo block convolutional code (CTBC) involves a serial concatenation of a outer block code B with an inner recursive convolutional code, joined together by a constrained interleaver type 2 (CI-2). The CI-2 interleaver is designed off line, and prior to VLSI design time. The present invention provides massively parallel systems, methods, and apparatus for use in CTBC encoding and decoding. For example, a massively parallel CTBC decoder is be implemented using N processors, each with local private memory, and each with local access to a one or more respective memory locations (e.g., registers) in one or more respective multiported memory banks that each hold extrinsic or related information used in CTBC code iterative SISO decoding. Both the arithmetic decoding operations and the CI-2 interleaving and deinterleaving functions are performed in parallel using the systems, methods, and apparatus of the present invention. |
| 主权项 |
1. A method for use in a parallel processing system, the method comprising:
distributing M respective subsequences of digitized received signal input information elements to M respective local memory banks, wherein each of the M respective local memory banks is coupled to a respective one of a set of M processors, wherein M is an integer and M>1; at each respective one of the M processors, performing, a respective pass of inner recursive convolutional code (IRCC) soft input soft output (SISO) decoding (IRCC SISO decoding) to produce a respective subsequence of IRCC SISO decoding output information elements; performing parallel constrained deinterleaving in order to distribute, in parallel, a plurality of the IRCC SISO decoding output information elements to a set of respective target memory locations located in respective target ones of a set of N multiport memory banks, wherein N is an integer and N≧M, wherein the plurality of IRCC SISO decoding output information elements include IRCC SISO decoding output information elements that were generated in a plurality of different ones of the M processors; at each respective one of the N processors, performing a respective pass of outer block code (OBC) SISO decoding (OBC SISO decoding) to produce a respective subsequence of OBC SISO decoding output information elements associated with one or more codewords of an outer block code, B; in the event that a stopping criterion has not been met, performing parallel constrained interleaving in order to distribute, in parallel, a plurality of OBC SISO decoding output information elements to a set of respective target memory locations located in respective target ones of a set of M multiport memory banks, and repeating the above recited actions, starting with the action of performing IRCC SISO decoding at each respective one of the M processors, until the stopping criterion is met, wherein the plurality of OBC SISO decoding output information elements include OBC SISO decoding output information elements that were generated in a plurality of different ones of the N processors; and in the event that the stopping criterion has been met, outputting a set of decoded message bits; wherein the M processors perform their respective passes of IRCC SISO decoding substantially in parallel with each other, and the N processors perform their respective passes of OBC SISO decoding substantially in parallel with each other; wherein the M processors are a member of the group consisting of M processors that are different from the N processors, and M processors that are a subset of the N processors; wherein the M multiport memory banks are a member of the group consisting of multiport memory banks different from the N multiport memory banks, and M multiport memory banks that are a subset of the N multiport memory banks, and wherein the stopping criterion is a member of the group consisting of performing a fixed number of the updating operations, and determining that a convergence criterion has been met. |
