发明名称 MULTIPLE PATTERNING DESIGN WITH REDUCED COMPLEXITY
摘要 A three color map can be built based on an integrated circuit (IC) layout, each color representing an exposure in a multiple (here triple) patterning lithography process and can include any combination of additive and/or subtractive exposures. A series of design rules can start with color-specific rules before considering any combination of colors and/or exposures. If the map fails any rule, building the map can be repeated with adjustments and it can be assessed with the design rules.
申请公布号 US2015234974(A1) 申请公布日期 2015.08.20
申请号 US201414181990 申请日期 2014.02.17
申请人 Samsung Electronics Co., Ltd. ;International Business Machines Corporation 发明人 Dechene Daniel J.;Kim Sutae;Lin Chieh-yu
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method, performed on a computing device having at least one processing unit in communication with at least one non-transitory computer readable storage medium, of preparing an integrated circuit (IC) layout design, the method comprising: using the at least one processing unit of the computing device to: receive a layout of the layout design with pattern features in the layout specified as discrete shapes;build a multiple color representation of the layout including a combination of a plurality of colors, each color representing a respective exposure, and each discrete shape of the layout including a subshape in at least one of the colors;determine whether the multiple color representation of the layout passes a plurality of design rules including at least a minimum space between facing parallel edges of adjacent shapes; andresponsive to failure under at least one design rule, adjust the layout and repeat the building of a multiple color representation and the determining whether the multiple color representation passes a plurality of design rules.
地址 Gyeonggi-do KR