SELF-ADAPTIVE COMPOSITE TUNNELING FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME

摘要

The present invention provides a tunneling field effect transistor and a method for fabricating the same which refer to a field effect transistor logic device and circuit in a CMOS ultra-large integrated circuit (ULSI). The inventive concept of the invention lies in that, in a case of an N-type transistor, a side portion of a doped source region adjacent to an edge of the control gate is further implanted with P+ impurities on a basis of the doped source region being initially doped N− impurities, so that the initial N− impurities in the implanted portion are completely compensated by the P+ impurities, and in a case of a P-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is implanted with N+ impurities on a basis of the doped source region being initially doped P− impurities, so that the initial P− impurities in the implanted portion are completely compensated by the N+ impurities. In the transistor, the source region is implanted twice with different doping concentrations, such that a large current characteristic of the MOSFET can be effectively combined to increase an on-state current of the transistor, and also, the threshold adjustment for the MOSFET portion and the TFET portion of the transistor can be achieved in a self-adaptive way.

主权项

1. A tunneling field effect transistor, comprising a control gate, a gate dielectric layer, a semiconductor substrate, a doped source region and a doped drain region, the doped source region and the doped drain region being located at both sides of the control gate, respectively, characterized in that,
in a case of an N-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is further implanted with P+ impurities on a basis of the doped source region being initially doped N− impurities, so that the initial N− impurities in the implanted portion are completely compensated by the P+ impurities, and the portion doped with the P+ impurities is spaced apart from edges of an active region in a width direction, and in a case of a P-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is further implanted with N+ impurities on a basis of the doped source region being initially doped P− impurities, so that the initial P− impurities in the implanted portion are completely compensated by the N+ impurities, and the portion doped with N+ impurities is spaced apart from edges of an active region in a width direction.