PIPELINE DEPTH EXPLORATION IN A REGISTER TRANSFER LEVEL DESIGN DESCRIPTION OF AN ELECTRONIC CIRCUIT

摘要

A list of input registers and output registers for a circuit design are provided. The circuit design is modified by traversing output connections paths for each input register and replacing any register in the output connection paths with a wire unless the register is a listed output register. An initial total cycle time value for the modified circuit design is determined. A gate level description for the modified circuit design is obtained by a macro synthesis with the initial total cycle time value. The total cycle time value for the modified circuit design is then varied in order to determine the theoretical limit of the modified circuit design. This theoretical limit is realized when negative slacks are present in a macro synthesis of the modified circuit design for a given total cycle time value. Based on this theoretical limit, the minimum pipeline depth of the circuit design is determined.

主权项

1. A method for pipeline depth exploration in a register transfer level design description of an electronic circuit, the method comprising:
providing a list of input registers and output registers for said circuit design to be modified; traversing output connections paths for each input register and replacing any register in said output connection paths by a respective wire unless said register is contained in said list of output registers; determining an initial total cycle time value for said modified registerless circuit design accounting for a register latch insertion delay time value; obtaining a gate level description for said modified circuit design by macro synthesis with said initial total cycle time value; and varying the total cycle time value for said modified circuit design to determine a theoretical limit of said modified circuit design; wherein said theoretical limit of said modified circuit design is realized when negative slacks are present in the macro synthesis of said gate level description for said modified circuit design with a corresponding total cycle time value.