MASK SHIFT RESISTANCE-INDUCTANCE METHOD FOR MULTIPLE PATTERNING MASK DESIGN AND A METHOD FOR PERFORMING THE SAME

摘要

A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.

主权项

1. A method comprising:
providing a layout of an integrated circuit design; generating, by a processor, a plurality of multiple patterning decompositions from the layout, wherein each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set; determining a maximum mask shift between the first mask and the second mask; and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift.