| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock control circuit, receiver, and communication apparatus capable of handling multi-data rates by suppressing deterioration in clock performance in a high-frequency band.SOLUTION: A clock control circuit includes: a first buffer 91 that buffers a first input clock pair Iclk 0, Iclk 180 in a multiphase clock and performs output Oclk 0, Oclk 180; a second buffer 92 that receives a second input clock pair Iclk 90, Iclk 270 in the multiphase clock and can perform control of whether buffering the second clock pair to perform output Oclk 270, Oclk 90 or performing output OUT 1, OUT 2 of a fixed level L/H; and a frequency multiplier 93 that performs logical operation on the output from the first buffer and the output from the second buffer and performs output Doclk 0, Doclk 180 of a first output clock pair based on a frequency (f/2) obtained by doubling a frequency (f/4) of the multiphase clock or a second output clock pair based on the same frequency (f/4) as that of the multiphase clock. |
