| 发明名称 |
MULTIPLEXER CIRCUIT, COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN PROGRAM FOR DESIGNING MULTIPLEXER CIRCUIT, AND APPARATUS FOR DESIGNING MULTIPLEXER CIRCUIT |
| 摘要 |
In a multiplexer circuit which loads N data segments (N is an integer of N<M) led by an arbitrary data segment from a first register storing M data segments (M is an integer equal to or larger than two) to a second register, an intermediate register is disposed between the first register and the second register. A first selection circuit between the first register and the intermediate register and a second selection circuit between the intermediate register and the second register are designed based on a value of L for minimizing a circuit amount of the first selection circuit and the second selection circuit. The value of L for minimizing the circuit amount is calculated based on values of the M and the N. Therefore, it is possible to reduce the circuit amount of the multiplexer circuit capable of performing data access with respect to large-volume data. |
| 申请公布号 |
US2015236684(A1) |
申请公布日期 |
2015.08.20 |
| 申请号 |
US201514605454 |
申请日期 |
2015.01.26 |
| 申请人 |
FUJITSU LIMITED |
发明人 |
Tamiya Yutaka |
| 分类号 |
H03K17/00 |
主分类号 |
H03K17/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A multiplexer circuit which loads N data segments (N is an integer of N<M) led by an arbitrary data segment from a first register storing M data segments (M is an integer equal to or larger than two) to a second register, the multiplexer circuit comprising:
an intermediate register configured to temporarily store L data segments (L is an integer of N<L<M) including the N data segments among the M data segments, between the first register and the second register; a first selection circuit configured to selectively load the L data segments among the M data segments from the first register to the intermediate register; and a second selection circuit configured to selectively load the N data segments among the L data segments from the intermediate register to the second register, wherein the first selection circuit and the second selection circuit are designed based on a value of L for minimizing a circuit amount of the first selection circuit and the second selection circuit, which is calculated according to values of the M and the N. |
| 地址 |
Kawasaki-shi JP |
