发明名称 Clock Dividing Device
摘要 A clock dividing device includes an accumulator that accumulates a first accumulated value and a denominator value and stores a second accumulated value, a register that stores a delayed accumulated value obtained by delaying the second accumulated value, a first comparison operation unit that performs a comparative operation on the second accumulated value and a numerator value and stores the second accumulated value as a greater value if the second accumulated value is greater than or equal to the numerator value, a second comparison operation unit that performs a comparative operation on the delayed accumulated value and the numerator value and stores the delayed accumulated value as a delay greater value if the delayed accumulated value is greater than or equal to the numerator value, and a third comparison operation unit that performs a comparative operation on the greater value and the delay greater value and determines the shape of a clock, wherein the shape of the clock is one of a bypass, a rising edge, and a falling edge.
申请公布号 US2015236701(A1) 申请公布日期 2015.08.20
申请号 US201414543921 申请日期 2014.11.18
申请人 Samsung Electronics Co., Ltd. 发明人 Song Jin-Ook
分类号 H03K21/02 主分类号 H03K21/02
代理机构 代理人
主权项 1. A clock dividing device comprising: an accumulator that is configured to sum a first accumulated value and a denominator value to generate a second accumulated value; a first comparison operation unit that is configured to perform a comparative operation on the second accumulated value and a numerator value and to store the second accumulated value as a greater value if the second accumulated value is greater than or equal to the numerator value and that is further configured to perform a comparative operation on a delayed accumulated value that is obtained by delaying the second accumulated value and the numerator value and to store the delayed accumulated value as a delayed greater value if the delayed accumulated value is greater than or equal to the numerator value; and a second comparison operation unit that is configured to perform a comparative operation on the greater value and the delayed greater value to determine a shape of a clock as one of a bypass, a rising edge, and a falling edge, wherein the numerator value is a value of a numerator of a frequency division ratio of the clock dividing device and the denominator value is a value of a denominator of the frequency division ratio of the clock dividing device.
地址 Suwon-si KR