BOUNDARY BASED POWER GUIDANCE FOR PHYSICAL SYNTHESIS

摘要

A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.

主权项

1. A method of obtaining a physical design of an integrated circuit from a logical design, the method comprising:
performing, with a processing device, a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget; computing power assertions; performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design; comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design; reducing a weighting of the power assertions relative to the timing constraints based on the degradation; and iteratively executing the performing the re-synthesis, the comparing, and the reducing until the degradation is below a threshold value.