发明名称 集積回路の並行検査の方法、装置及びシステム
摘要 <p>A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.</p>
申请公布号 JP5765889(B2) 申请公布日期 2015.08.19
申请号 JP20100063183 申请日期 2010.03.18
申请人 发明人
分类号 G01R31/28;G01R31/302;H01L21/66;H01L21/822;H01L27/04 主分类号 G01R31/28
代理机构 代理人
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