Strained transistor integration for CMOS

摘要

Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

主权项

1. An apparatus comprising:
a first layer of a silicon material suitable as a first channel for a first circuit device on a first interface surface of a first silicon alloy material; wherein a lattice spacing of the silicon material is smaller than a lattice spacing of the first silicon alloy material at the first interface surface; a second layer of a second silicon alloy material suitable as a second channel for a second circuit device on a second interface surface of the first silicon alloy material; wherein a lattice spacing of the second silicon alloy material is larger than a lattice spacing of the first silicon alloy material at the second interface surface, wherein the second silicon alloy material has between 10 and 30 percent more Germanium than the first silicon alloy material, wherein the first silicon alloy material is a substrate of graded relaxed silicon Germanium material; and wherein the graded relaxed silicon Germanium material has one of (1) a thickness of between 1 micrometer and 3 micrometers in thickness, and a grading concentration of Germanium that increases from 0 percent to between 10 percent and 30 percent at the first and second interface surfaces, or (2) a grading concentration rate that increases at between 5 percent Ge and 15 percent Ge per micrometer in a direction towards the first and second interface surfaces; and a gate dielectric layer in contact with the Silicon material and the second Silicon alloy material.