FET dielectric reliability enhancement

摘要

A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

主权项

1. A semiconductor device, comprising:
a substrate which has a semiconductor layer disposed over a top surface of said substrate; a gate dielectric layer disposed over said semiconductor layer, said gate dielectric layer containing silicon; a metal gate disposed over said gate dielectric layer, said metal gate including 2 atomic percent to 10 atomic percent silicon; and contact metal disposed in source and drain contact holes proximate to said metal gate.