发明名称 |
Embedded package and method for manufacturing the same |
摘要 |
An embedded package includes a semiconductor chip divided into a cell region and a peripheral region, having a first surface and a second surface which faces away from the first surface, and including an integrated circuit which is formed in the cell region on the first surface, a bonding pad which is formed in the peripheral region on the first surface and a bump which is formed over the bonding pad; a core layer attached to the second surface of the to semiconductor chip; an insulation component formed over the core layer including the semiconductor chip and having an opening which exposes the bump; and a circuit wiring line formed over the insulation component and the bump and electrically connected to the bump, wherein the insulation component formed in the cell region has a thickness larger than a height of the bump. |
申请公布号 |
US9111820(B2) |
申请公布日期 |
2015.08.18 |
申请号 |
US201414217624 |
申请日期 |
2014.03.18 |
申请人 |
SK Hynix Inc. |
发明人 |
Chung Qwan Ho |
分类号 |
H01L23/498;H01L23/48;H01L21/56;H01L23/00;H01L23/31 |
主分类号 |
H01L23/498 |
代理机构 |
William Park & Associates Ltd. |
代理人 |
William Park & Associates Ltd. |
主权项 |
1. An embedded package comprising:
a semiconductor chip having a first surface and a second surface, the first surface including a cell region and a peripheral region, wherein an integrated circuit is formed in the cell region; and wherein a bonding pad having a bump formed thereon is formed in the peripheral region; an insulation component formed over the first surface while exposing the bump therethrough; and a circuit wiring line formed over the insulation component and the bump, wherein the bump is coupled to the circuit wiring line, and wherein the circuit wiring line comprises a first portion of the circuit wiring line formed on the cell region, and a second portion of the circuit wiring line formed on the peripheral region, wherein the insulation component comprises a first portion of the insulation component disposed between the first portion of the circuit wiring line and the first surface of the semiconductor chip, and a second portion of the insulation component disposed between the second portion of the circuit wiring line and the first surface of the semiconductor chip, and wherein a thickness of the first portion of the insulation component is larger than a thickness of the second portion of the insulation component. |
地址 |
Gyeonggi-do KR |