发明名称 |
MRAM smart bit write algorithm with error correction parity bits |
摘要 |
Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location. |
申请公布号 |
US9110829(B2) |
申请公布日期 |
2015.08.18 |
申请号 |
US201313917772 |
申请日期 |
2013.06.14 |
申请人 |
Taiwan Semiconductor Manufacturing Co. Ltd. |
发明人 |
Chih Yue-Der;Yu Hung-Chang;Lin Kai-Chun;Huang Chin-Yi;Tran Laun C. |
分类号 |
G11C29/00;H03M13/00;G06F11/10;G06F11/14;G11C11/16;G11C13/00 |
主分类号 |
G11C29/00 |
代理机构 |
Eschweiler & Associates, LLC |
代理人 |
Eschweiler & Associates, LLC |
主权项 |
1. A method, comprising:
attempting to write an expected multi-bit word to a memory location in a magnetic random access memory (MRAM); after attempting to write the multi-bit word, reading an actual multi-bit word from the memory location; logically comparing the actual multi-bit word with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location; based on a result of the logical comparison, attempting to selectively re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location. |
地址 |
Hsin-Chu TW |