Temperature dependent biasing for leakage power reduction

摘要

Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and where the voltage has a value outside of a voltage supply range of the logic circuit. In another embodiment, a semiconductor device may include a biasing circuit configured to generate a voltage that varies according to a temperature of the semiconductor device and a power switch operably coupled to the biasing circuit, where the voltage is applied to a gate terminal of the power switch, and where the voltage has a value outside of a voltage supply range of the power switch.

主权项

1. A semiconductor device, comprising:
a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device, wherein a magnitude of the voltage increases in response to an increase in the temperature of the semiconductor device, and wherein the magnitude of the voltage decreases in response to the temperature of the semiconductor device decreasing; and a logic circuit operably coupled to the biasing circuit, wherein the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and wherein the voltage has a value outside of a voltage supply range of the logic circuit, wherein the biasing circuit further comprises: a first current mirror including two PMOS transistors, a second current mirror including two NMOS transistors operably coupled to the first current mirror, and a resistor operably coupled to the second current mirror, wherein a current through one of the two NMOS transistors is proportional to the temperature of the semiconductor device, and wherein the voltage is provided to the bulk terminal by a node between a source terminal of the one of the two NMOS transistors and the resistor.