Method and system for forward error correction of interleaved-formated data

摘要

In one embodiment, a device is provided. The device includes a first formatting circuit configured to add zero padding bits to a received data block. An FEC encoder circuit is coupled to the first formatting circuit and is configured to determine parity bits for the data block at a first code rate. A second formatting circuit is coupled to the FEC encoder circuit and is configured to combine the parity bits with the data block and remove the zero padding bits to provide an FEC coded data block at a second code rate. The second code rate is less than the first code rate.

主权项

1. A device, comprising:
a first formatting circuit configured to add zero padding bits to a received data block; a forward error correction (FEC) encoder circuit coupled to the first formatting circuit and configured to determine parity bits for the data block at a first code rate; and a second formatting circuit coupled to the FEC encoder circuit and configured to combine the parity bits with the data block and remove the zero padding bits to provide an FEC coded data block at a second code rate, the second code rate being less than the first code rate; wherein the first formatting circuit includes:
a row de-interleaver circuit configured to format the received data block into a row-aligned format, wherein each row of the data block in the row-aligned format includes data bits equal to data bits in a corresponding row in a de-interleaved format; anda column de-interleaver circuit configured to format the received data block into a column-aligned format, wherein each row of the data block in the column-aligned format includes data bits equal to data bits in a corresponding column in the de-interleaved format; the FEC encoder circuit includes:
a row encoding circuit coupled to the first formatting circuit and configured to perform FEC coding on the rows of the data block in the row-aligned format to produce a row-coded data block; anda column encoding circuit coupled to the second formatting circuit and configured to perform FEC coding on rows of the data block in the column-aligned format, the rows corresponding to respective columns of the data block in the de-interleaved format, to produce a column-coded data block; andthe second formatting circuit is configured to combine the row-coded data block and the column-coded data block to produce an FEC coded data block and remove the zero padding bits.