Method of reading and writing to a spin torque magnetic random access memory with error correcting code

摘要

A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort.

主权项

1. A method comprising: calculating a plurality of Error Correction Code (ECC) bits associated with an ECC word of a memory array, the ECC word associated with a plurality of data bits and each ECC bit of the plurality of ECC bits is calculated using an even number of data bits of the plurality of data bits associated with the ECC word;
storing the plurality of ECC bits in the memory array; determining a majority state associated with the plurality of data bits; inverting the plurality of data bits to provide a plurality of inverted data bits based at least in part on the majority state of the plurality of data bits; storing the plurality of inverted data bits in the memory array; storing at least one inversion status bit in the memory array; reading the stored plurality of inverted data bits, the stored plurality of ECC bits, and the stored at least one inversion status bit from the memory array; calculating each parity bit of a plurality of parity bits using an even number of data bits of the stored plurality of data bits read from the memory array; detecting at least one error in the plurality of inverted data bits based at least in part on a comparison of the plurality of parity bits and the plurality of ECC bits; detecting at least one error in the plurality of ECC bits based at least in part on a comparison of the plurality of parity bits and the plurality of ECC bits; generating a plurality of corrected ECC bits using the plurality of parity bits and the stored plurality of ECC bits read from the memory; generating a plurality of corrected data bits; and inverting the plurality of corrected data bits based at least in part on the state of the at least one inversion status bit.