Electrostatic discharge circuit

摘要

An integrated circuit is provided. The integrated circuit may include, but is not limited to, a first node, a second node configured to be coupled to ground, an output driver, and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver. The electrostatic discharge circuit may include, but is not limited a high-pass filter configured to detect an electrostatic discharge event at the first node, a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, and a step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit.

主权项

1. An integrated circuit, comprising:
a first node configured to receive an input or an output; a second node configured to be coupled to a reference voltage; an output driver electrically coupled to the first node and the second node; and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver, the electrostatic discharge circuit comprising:
a high-pass filter configured to detect an electrostatic discharge event at the first node;a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, the driving stage circuit comprising:
a first transistor including a gate, a source, and a drain, wherein the drain of the first transistor is coupled to the first node and the gate of the first transistor is coupled to the high-pass filter;a second transistor including a gate, a source, and a drain, wherein the source of the second transistor is coupled to the source of the first transistor and the gate of the second transistor is coupled to the step-down circuit;a third transistor including a gate, a source, and a drain, wherein the drain of the third transistor is coupled to the drain of the second transistor, the gate of the third transistor is coupled to the step-down circuit, and the source of the third transistor is coupled to the second node; anda fourth transistor including a gate, a source, and a drain, wherein the gate of the fourth transistor is coupled to the drain of the second transistor, the source of the fourth transistor is coupled to the second node and the drain of the fourth transistor is coupled to the output driver;a latch circuit electrically coupled to the driving stage circuit, the latch circuit configured to increase a rate the driving stage circuit shunts the output driver to the second node in response to the signal from the high-pass filter, the latch circuit comprising:
a fifth transistor including a gate, a source, and a drain, wherein the gate of the fifth transistor is coupled to the gate of the third transistor, a source of the fifth transistor is coupled to the second node and a drain of the fifth transistor is coupled to a gate of the first transistor;a sixth transistor including a gate, a source, and a drain, wherein the gate of the sixth transistor is coupled to the gate of the fourth transistor, the source of the sixth transistor is coupled to the second node and the drain of the sixth transistor is coupled to the step-down circuit; anda first resistor including a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the second node and the second terminal of the first resistor is coupled to the gate of the fourth transistor; anda step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit.