Low voltage level shifter for low power applications

摘要

A level shifter circuit for low power applications that can shift the level of a digital signal that is below the threshold voltage of output transistors. The level shifter uses core transistors in the input stage and includes an intermediate stage that limits the voltage applied to the drain of the core transistors. The intermediate stage may include two transistors whose gate is connected to a reference voltage and turns off when the voltage at their source is equal to a threshold voltage below the reference voltage, thus limiting the maximum voltage applied to the transistors present in the input stage.

主权项

1. A non-transitory computer readable medium storing a digital representation of level shifter circuit, the level shifter circuit comprising:
an input stage configured to receive an input signal from an input terminal changing in a first voltage range, and comprising:
a first transistor having a gate receiving the input signal, the first transistor turned on responsive to the input signal being active and turned off responsive to the input signal being inactive, anda second transistor having a gate receiving an inverse of the input signal, the second transistor turned on responsive to the input signal being inactive and turned off responsive to the input signal being active; an intermediate stage coupled to the input stage and configured to regulate a voltage of an intermediate signal generated in response to operation of the input stage, the intermediate stage comprising:
a third transistor having a gate receiving a reference voltage and a source coupled to a drain of the first transistor,a fourth transistor having a gate receiving the reference voltage and a source coupled to a drain of the second transistor,a fifth transistor coupled to the third transistor,a first voltage divider configured to bias the fifth transistor by dividing a voltage between a drain of the fifth transistor and a source of the fifth transistor, an output of the first voltage divider coupled to a gate of the fifth transistor,an sixth transistor coupled to the forth transistor, anda second voltage divider configured to bias the sixth transistor by dividing a voltage between a drain of the sixth transistor and a source of the sixth transistor, an output of the second voltage divider coupled to a gate of the sixth transistor,wherein a threshold voltage of the fifth transistor and the sixth transistor is larger than first voltage range; and an output stage coupled to the intermediate stage, the output stage configured to generate an output signal changing at a second voltage range higher than the first voltage range based on the intermediate signal.